The invention pertains to a device structure and method for making JFET transistors at very small line widths which can overcome certain process problems in CMOS circuits built with small line widths.
As line widths have shrunk steadily down into the submicron range (today's line widths are 45 nanometers or 0.045 microns where a micron is 10−6 meters and one nanometer equals 10 angstroms), all structures on CMOS, NMOS and PMOS circuits have shrunk including the thickness of the gate oxide. As line widths shrink, the voltages must be dropped to avoid punch through. This shrinking line width means smaller gate length which requires that the thickness of gate oxide must also be reduced to allow proper control of the current flow in MOS devices at the lower voltages. Reduced gate oxide thickness results in increased gate capacitance per unit area which has to be switched. Since smaller geometries imply increased circuit density, the result is an overall increase in the power needed for to operate the chip. In addition, shrinking gate oxide thickness causes leakage which increases power consumption in CMOS circuits and all other MOS circuits. The limit of gate oxide thickness that will not cause leakage is about 30 nanometers, which was used in older technologies with minimum line widths of 10 NM while 45 nanometer line widths (0.045 microns) are the state of the art now.
At one micron line widths, power consumption for a one square centimeter integrated circuit was 5 watts. As line widths shrank to 45 nanometers, power consumption for the same size chip rose to 1000 watts. This can destroy an integrated circuit which is not cooled properly and is unacceptable for portable devices such as laptops, cell phones etc. This power consumption complicates the design process immensely because it requires circuitry to put transistors that are not working to sleep so they do not waste power.
Prior art junction field effect transistors date back to the 1950's when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows:
1) Nanver and Goudena, “Design Considerations for Integrated High-Frequency P-Channel JFET's”, IEEE Transactions Electron Devices, Vol;. 35, No. 11, 10 1988, pp. 1924-1933.
2) Ozawa, “electrical Properties of a Triode Like Silicon Vertical Channel JFET”, IEEE Transactions Electron Devices Vol. ED-27, No. 11, 1980, pp. 21152123.
3) H. Takanagi and G. Kano, “Complementary JFET Negative-Resistance 15 Devices”, IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, Dec 1975, pp. 509-515. 4) A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel Analog Multiplexer”, IEEE Journal of Solid State Circuits, Vol. SC-16, No. 6, Dec 1978. 5) K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, 20 IEE Transaction on Electron Devices, Vol. ED-27, No. 6, Jun 1980. In addition, a report published by R. Zuleeg titled “Complimentary GaAs Logic” dated 4 Aug. 1985 is cited herein as prior art.
A representative structure of a conventional, prior art n-channel JFET is shown in FIG. 1. The JFET is formed in an n-type substrate 810. It is contained in a p-well region marked 815. The body of the JFET is shown as 820, which is an n-type diffused region containing source (832), channel (838), and drain (834) regions. The gate region (836) is p-type, formed by diffusion into the substrate. Contacts to the source, drain, and gate regions are marked as 841, 842, and 840, respectively. The critical dimension of the JFET is the gate length, marked as 855. It is determined by the minimum contact hole dimension 850, plus the necessary design rules overlap required to ensure that the gate region encloses the gate contact. The gate length 855 is significantly larger than 850. This feature of construction of the prior art JFET limits the performance of these devices, since channel length is substantially larger than the minimum feature size. In addition, the capacitances of the vertical sidewalls 861 and 862 of the gate diffusion 836 to drain and source regions 832 and 834, respectively, are also quite large. The gate—drain sidewall capacitance forms the Miller capacitance, a term known to those skilled in the art, and significantly limits the performance of the device at high frequencies.
In order to substitute JFETs for CMOS to solve the power consumption problem at line widths of 45 NM and smaller, it is necessary to have a normally off JFET with very small gate capacitance in comparison to MOS transistors of comparable geometry, and with very small parasitic capacitance. It is also desirable to have a self aligned gate in such JFET devices with respect to the channel. It is therefore desirable to be able to fabricate the gate electrode without using a mask by etching a self aligned hole in spacer oxide to achieve these targets.
One solution to the increasing power consumption problem of conventional CMOS as line widths shrink is the normally off junction field effect transistor or JFET which was invented by Ashok Kapoor and described in a patent application entitled Complementary Junction Field Effect Transistor Circuit in Silicon and Silicon Alloys, filed Oct. 28, 2005, Ser. No. 11/261,873, which is hereby incorporated by reference. A conventional normally-on JFET looks like the structure shown in FIG. 1.
One embodiment of Dr. Kapoor's JFET structure is shown in FIG. 2. This figure is a cross section of a N-channel JFET which has had its doping levels and dimensions designed such that it operates in mode. The JFET has four terminal regions in the substrate and corresponding contacts above the substrate surface. The terminal regions in the substrate are: source 31 (comprised of a diffusion region under polysilicon contact 72 and an implanted region coupling the diffused region to the channel region 50); gate 70; drain 40 (comprised of a diffusion region under polysilicon contact 74 and an implanted region coupling the diffused region to the channel region 50) and P-well 11 which has an ohmic contact region shown at 68. The contacts to the source, drain, gate and P-well regions are made of polysilicon typically and are: substrate contact 71, source contact 72; gate contact 75 and drain contact 74. The JFET is formed in a region of silicon substrate 15 in FIG. 2. The JFET is isolated from the surrounding semiconductor by insulating regions 21, which are typically Shallow Trench Isolation (hereafter STI) field oxide. The channel between the source and drain is shown at 50. For an N-channel JFET, the source and drain regions 31 and 40 are N+ regions (highly doped with N type donor impurities such as phosphorous, arsenic or antimony). The P well 11 is doped P type with acceptor impurities such as boron or indium. Contact to the P well is formed by poly contact 71 which is doped heavily P type and which, by diffusion during the drive in process to form the gate, forms an ohmic contact and a P+ region 68 which acts as the P well contact by virtue of the configuration of the field oxide regions 21 as shown. The field oxide regions must not extend below the depth of the P well to substrate junction 87 so as to not cut off a conductive path from the ohmic contact 68 to the P well portion 11 under the channel region 50. The channel is a narrow region 50 which is doped lightly N type. The gate is a very shallow (typically 10 nanometers, hereafter NM) P type region formed in the N type channel by methods such as diffusion of dopants from the overlying heavily P+ doped polysilicon 75 or ion implantation. A doping profile of the transistor at varying depths from the surface through the gate 70 and channel 50 is shown in FIG. 3. The drive-in process to form the gate region 70 and the implant to form the channel region 50 are both important because the depth of these regions and their doping must be controlled so that the depletion regions of the gate-channel junction and the channel-P well junction formed with zero volt external bias on gate and well with respect to source touch so as to cause pinch off. Curve 81 is a typical gate doping profile and point 85 is typically only about 10 NM from the substrate surface so the gate is very shallow. This requirement is a significant part of the solution to the problem that the invention solves. Curves 82, 83 and 84 represent the doping profile of the channel 50, the P well 11 and the substrate bulk regions 15 respectively. The depth of the gate-channel junction is at point 85. The depth of the channel-P well junction is at point 86 and is typically only 40 NM down from the surface of the substrate. The depth of the well-substrate junction is shown at 87. Each junction has a depletion region on either side of the junction even when the junction has zero bias across it.
As alluded to earlier, the key to designing a normally off or enhancement mode JFET is to design the device such that the depletion region surrounding the gate-channel junction 85 to be large enough to extend down to the boundary of the depletion region surrounding the channel-well junction 86 (or channel-substrate junction 86 in the case of embodiments of FIGS. 5C and 15). This pinches off current flow when the gate bias is zero volts thereby making an enhancement mode device. The depletion regions around each junction have a fixed width at zero bias. How far above and below a PN junction the depletion region spreads depends upon the relative doping concentration of the semiconductor above and below the junction. The doping concentration of the regions on either side of junctions 85 and 86 and the size of the gate and channel regions are coordinated so that pinch off occurs.
FIG. 4 is a blown up view of the gate and channel regions showing the boundaries 90 and 91 of the depletion region around the gate-channel junction 85 in a conventional normally-on JFET. The depletion region around the channel-well junction 86 is marked by an upper boundary 92 and a lower boundary 94. The boundary 91 in the channel region 50 is nearly coincident with the upper boundary 92 of the depletion region around the channel-P well junction 86, but because they are not coincident, no pinchoff occurs, and current flows in the neutral region. When the doping of the gate, channel and will regions and junction depths are such as to cause this condition shown in FIG. 4, the device is called a normally on or depletion mode device because it takes some gate bias to turn off current flow from the source to the drain by causing pinchoff, i.e., a condition where the depletion region boundary 91 meets the depletion region boundary 92. Conversely, the doping of the gate, channel and well regions and the junction depths can be controlled so as to cause pinchoff at a much smaller positive or zero gate bias, and such a device is called a normally off or enhancement mode device. More specifically, in a JFET, the doping of the channel region versus the doping of the gate region and the relative depths of the gate-channel junction 85 versus the channel-P well junction and the doping of the semiconductor under junction 86 can all be controlled such that boundary 91 touches boundary 92 at zero gate bias or a gate bias of less than one volt. This causes pinch off so very little current flows from source 31 to drain 40 through channel 50. When a positive bias is applied across the gate-channel junction to reduce the width of the depletion region, it takes the device out of pinchoff so as to allow conduction between the source and drain.
The JFET of FIG. 2 requires two separate masks to dope the single polysilicon layer so that the portions over the source and drain can be doped N+ and the portions over the gate and P well contact can be doped P+. As feature sizes get smaller, alignment of features created by different mask layers becomes more difficult and design rule tolerances eat up valuable chip real estate. It is desirable to reduce the area of the JFET by doing a dual conductive semiconducting layer deposition with a self-aligned gate contact to reduce device area hereafter referred to as a “dual poly” process even though the first conductive layer from which the source and drain contacts are formed need not be polysilicon and can be metal. Dual poly bipolar devices are known so there is a large body of knowledge on how to do dual poly construction. However, to the applicant's knowledge, no dual poly JFET integration processes exist.
Therefore, a need has arisen for a method of building a JFET which has low parasitic capacitances, reduces the number of masks involved in the process for polysilicon processing and which results in formation of a self-aligned gate contact.